This application relies for priority upon Korean Patent Application No. 2000-63396, filed on Oct. 27, 2000, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to semiconductor devices and fabrication methods thereof and, more particularly, to non-volatile memory devices and to fabrication methods thereof.
A non-volatile memory device is an advanced type of memory device that retains information stored in its memory cells even when no power is supplied. Nowadays, the non-volatile memory device is widely used in various kinds of electronics product like as a cellular phone, a memory card and so on.
The non-volatile memory device generally comprises a cell array area and a peripheral circuit area. The cell array area is comprises a plurality of memory cells organized in a two-dimensional matrix. That is to say, the cells are organized in rows and columns. Unit cells are located at the respective intersections formed by a plurality of word lines and a plurality of bit lines in the matrix. The peripheral circuit area is generally formed to surround the cell array area. In the peripheral circuit area, there is circuitry for performing a programming operation, a reading operation, an erasure operation and so on. A stacked gate cell is used as a unit cell of a number of non-volatile memory devices with an advantage of its small cell size (surface area). The stacked gate cell has a floating gate electrode and a control gate electrode. Typically, the control gate electrode is stacked on the floating gate electrode.
FIGS. 1 to 4 are cross-sectional views illustrating a process for forming a non-volatile memory device according to the prior art. A cell array area and a peripheral circuit area are denoted by bracketed regions xe2x80x9caxe2x80x9d and xe2x80x9cbxe2x80x9d respectively. For a better understanding of problems in the prior art, the cross-sectional views in the cell array area are taken along a line between and parallel to the control gate electrodes of the cell array. The control gate electrodes act as the word lines during operation of the device. The cross-sectional views in the peripheral circuit area are taken across a gate electrode of a transistor.
Referring to FIG. 1, an isolation region 3 is formed in a semiconductor substrate 1, thereby defining active regions in the substrate 1. The isolation region 3 surrounds the active regions. A tunnel oxide layer 5 is formed on the surface of the active regions with a thickness of 100 xc3x85 or less. A first conductive layer 7 is formed on a surface of the resultant structure. The first conductive layer is patterned to form floating gate patterns 7a in the cell array area, and to form a gate electrode pattern 7b in the peripheral circuit area. It is preferable that sidewalls of the floating gate patterns 7a have inclinations with complementary positive and negative slopes to the substrate as shown in the figure. These sidewall inclinations are helpful to prevent voids from forming between the floating gate patterns 7a during subsequent process steps.
An inter-gate insulating layer 9 is formed on a surface of the resultant structure having the floating gate patterns 7a and the gate electrode pattern 7b. The inter-gate insulating layer 9 has a thickness T1 along a sidewall of the floating gate patterns 7a and a thickness T2 on a top surface of the gate electrode pattern 7b. Thickness T1 is measured vertically to the surface plane of the substrate 1. Thickness T1 is much greater than thickness T2. This is due to the inclination of the sidewall of the floating gate patterns 7a. 
Referring to FIG. 2, a second conductive layer 11 is formed on a surface of the resultant structure. Photoresist patterns 13 are formed on the second conductive layer 11. The photoresist patterns 13 are for patterning the control gate electrodes of the cell array (though not shown) and the gate electrode of a transistor of the peripheral area. Because the cross-sectional views in the cell array area are taken along the line between and parallel to the control gate electrodes of the cell array, as described above, there is no photoresist pattern shown in the cell array area of the figure.
Referring to FIG. 3, the second conductive layer 11 and the inter-gate insulating layer 9 are etched continuously using the photoresist patterns 13 as etch masks by anisotropic dry etching to form the control gate electrodes (though not shown) and a dummy gate electrode 11d. There may result over-etching in the gate electrode pattern 7b, causing a considerably recessed gate electrode pattern 7bxe2x80x2. An etch time to completely remove the inter-gate insulating layer 9 in the cell array area is greater than an etch time to completely remove the inter-gate insulating layer 9 in the peripheral circuit area. This is due to a unique anisotropic characteristic of the etching and the thickness difference between thickness T1 and thickness T2. Moreover, an etch rate in the relatively dense cell array area is greater than an etch rate in the relatively sparse peripheral circuit area. This etch rate difference is known as a loading effect in dry etching technique. For the reasons described above, there may be some recession D shown in FIG. 3. In other words, the thickness of the floating gate patterns 7a may be greater than a thickness of the recessed gate electrode pattern 7bxe2x80x2 just after forming the control gate electrodes and the dummy gate electrode 11d. 
Referring to FIG. 4, the floating gate patterns 7a and the recessed gate electrode pattern 7bxe2x80x2 are etched using the photoresist patterns 13 as etch masks to form floating gate electrodes (though not shown) and gate electrode 7g. As shown in the figure, there may be some crystalline defect A after the forming the floating gate electrodes (though not shown) and the gate electrode 7g. The crystalline defect results from etch damage on the substrate 1. This is because of the thickness difference between the floating gate patterns 7a and the recessed gate electrode pattern 7b. Such a crystalline defect A on the silicon substrate is known to induce undesirable leakage current in a semiconductor device.
It is an object of the present invention to provide a non-volatile memory device having no crystalline defect on a semiconductor substrate.
Another object of the present invention is to provide a method for forming a non-volatile memory device, which can prevent over-etching in forming a gate electrode in a peripheral circuit area and a floating gate electrode in a cell array area.
According to one aspect of the present invention, a non-volatile memory device is provided. The non-volatile memory device comprises first and second active regions formed in a semiconductor substrate and defined by an isolation region. A control gate electrode is disposed across the first active region, and a floating gate electrode intervenes between the control gate electrode and the first active region. A first inter-gate insulating layer intervenes between the control gate electrode and the floating gate electrode. A gate electrode is disposed across the second active region. A dummy gate electrode is disposed on the gate electrode. A second inter-gate insulating layer intervenes between the gate electrode and the dummy gate electrode. The second inter-gate insulating layer is thicker than the first inter-gate insulating layer.
According to another aspect of the present invention, a semiconductor device is provided. The semiconductor device comprises a dense area and a sparse area in a semiconductor substrate. A first active region is formed in the dense area. A second active region is formed in the sparse area. A first conductive layer is formed on the first and the second active regions. A second conductive layer is formed on the first conductive layer. A silicon nitride layer intervenes between the first conductive layer and the second conductive layer, and a composite insulating layer intervenes between the second conductive layer and the silicon nitride layer. A portion of the composite insulating layer on the second active region is thicker than another portion of the composite insulating layer on the first active region.
According to another aspect of the invention, a method of forming a nonvolatile memory device is provided. This method comprises providing a semiconductor substrate having a cell array area and a peripheral circuit area. An isolation region is formed to define a first active region and second active regions in the cell array area and the peripheral circuit area respectively. A tunnel oxide layer is formed on the first and the second active regions. A first conductive layer is formed on the resultant structure having the tunnel oxide layer. The first conductive layer is patterned to form a floating gate pattern on the first active region and a gate electrode pattern on the second active region. First and second inter-gate insulating layers are formed on the floating gate pattern and the gate electrode pattern respectively. The second inter-gate insulating layer is thicker than the first inter-gate insulating layer. A second conductive layer is formed on the first inter-gate insulating layer and the second inter-gate insulating layer.
Accordingly, it is possible to reduce any undesirable difference between the thickness of the first inter-gate insulating layer on a sidewall of the floating gate patterns and the thickness of the first inter-gate insulating layer on the gate electrode pattern. It is also possible to prevent over-etching when forming a gate electrode in a peripheral circuit area and a floating gate electrode in a cell array area.